[PDF.87mu] Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

[PDF.ko98] Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Design-for-Test and Test Optimization  Brandon Noia, Krishnendu Chakrabarty epub
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 | #5963716 in Books |  2013-11-16 | Original language:English | PDF # 1 |  9.20 x.80 x6.00l,1.45 | File type: PDF | 245 pages

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||From the Back Cover||This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC tes

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimizati...

You easily download any file type for your gadget.Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs   |  Brandon Noia, Krishnendu Chakrabarty. A good, fresh read, highly recommended.

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